Code Generation for a Runtime Configurable Loop Coprocessor

The idea of parallelizing loops using Single Kernel Modulo Scheduling on a high specialized coprocessor is attractive. We use a multiclustered Scalar Operand Network as coprocessor, where the topology of the net is reconfigurable.

Since the cluster assignment and the scheduling passes are performed statically, the compiler has to generate the reconfiguration instructions which adapt at the best, at run-time, the topology of the net to the currently scheduled DDG.

This project aims at investigating how to design an architecture which schedules successfully the large part of a program, exploting also the reconfigurability for both the goals to guarantee scalability and improve the quality of the schedule.

Goals achieved so far are the proposal of a novel approach to attack the problem of Instruction Partitioning over a Hierarchical Machine Model and its implementation in a Clustering Tool – which will become part of an industrial compilation toolchain for DSPFabric, a multicluster architecture designed by STMicroelectronics, Grenoble.


  1. Martino Sykora, Davide Pavoni, Joel Cambonie, Roberto Costa, Stefano Crespi-Reghizzi: “Hierarchical Cluster Assignment for Coarse-Grain Reconfigurable Coprocessors”. IPDPS 2007, Long Beach, Mar 2007.
  2. M. Sykora. PhD Dissertation, Politecnico di Milano, 2007
research/rcp.txt · Last modified: 2010/07/07 12:16 (external edit)
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